In fields of optical communication, optical measurement, optical information processing or the like, faster and larger capacity communication is essential, and in particular, developments of semiconductor light receiving elements with enhanced faster response are indispensable in the field of the light receiving elements. Increased reliability, reduced cost and further increased productivity are required in these semiconductor light receiving elements, as well as enhanced device characteristics. Typical examples of semiconductor light receiving elements for the use in the wave length of 1 to 1.6 μm band include PIN photodiodes (hereinafter referred to as “PIN-PD”) composed of compound semiconductors (see, for example, Non-Patent Documents 1 and 2), avalanche photodiodes (hereinafter referred to as “APD”) (see, for example, Non-Patent Document 3 and Patent Document 1), and the like. A planar structure or a pseudo planar structure as described in Non-Patent Documents 1 and 3 or a mesa structure as described in Non-Patent Document 2 and Patent Document 1 are adopted in these semiconductor light receiving elements. The semiconductor light receiving element having a planar structure or a pseudo planar structure is configured without exposing the semiconductor layer such as, for example, a multiplication layer of the APD or the like, which is applied with larger electric field, or a photo-absorption layer or the like, in which tunneling current is easily generated in the narrow gap. Thus, such structure is more advantageous as compared with the mesa structure semiconductor light receiving element, in view of providing higher reliability. However, a formation of a guard ring by an ion implantation process is indispensable for the planar structure semiconductor light receiving element, in order to inhibit a multiplication in the edge in a peripheral region of a light receiving unit. Therefore, flexibility for the structural design is generally limited in the semiconductor light receiving element having the planar structure, and the manufacturing process tends to be complicated. This results in causing a problem of difficulties in providing simple manufacture, lower cost, improvement in the device characteristics or the like, which are critical in the practical use.
On the contrary, the semiconductor light receiving element having the mesa structure involves the formation of the light receiving region by an etching process, and therefore manufacturing process for such device is simple, and thus is advantageous in achieving the cost reduction. Further, since a p-n junction is formed with an epitaxial growth process, the device characteristic can be easily controlled, and higher flexibility is achieved in the structural design, as compared with the semiconductor light receiving element having the planar structure. In addition, since an ion implantation process or a diffusion process is not required, higher reproducibility in the device characteristics and in the manufacturing process is achieved. However, in the semiconductor light receiving element having the mesa structure, side surfaces of semiconductor layers 703 to 707 such as a multiplication layer 703 or a photo-absorption layer 705 or the like are exposed in a side surface of the light receiving region having the mesa structure (hereinafter referred to as “mesa side surface”) similarly as in, for example, the APD shown in FIG. 9, and therefore a protective film 711 for covering these exposed sections is required to be formed. Conventionally such protective film 711 is known as the method for forming thereof with an insulating film of an organic compound such as a polyimide resin film, a benzocyclobutene resin film and the like, or an insulating film of an inorganic compound such as a silicon nitride film, a silicon oxide films and the like. Here, in FIG. 9, reference numeral 712 indicates an antireflection AR coating, 701 indicates a substrate, 702 indicates a buffer layer, 704 indicates a field buffer layer, 706 indicates a cap layer, 707 indicates a contact layer, and 708 and 709 indicate electrodes.    [Patent Document 1]    Japanese Patent Laid-Open No. 2000-22, 197    [Non-Patent Document 1]    ELECTRONICS LETTERS, Vol. 20, No. 16, pp. 654-656, 1984    [Non-Patent Document 2]    IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 50, No. 2, pp. 532-534, 2003    [Non-Patent Document 3]    IEEE PHOTONICS TECHNOLOGY LETTERS, Vol. 8, No. 6, pp. 827-829, 1996